Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to an internal voltage generator of a semiconductor device.
As semiconductor devices have been developed toward high-speed operation, low power consumption, and ultra fineness, operating voltages have also further lowered. Most semiconductor devices include an internal voltage generator configured to generate an internal voltage by using an external power supply voltage, so that the semiconductor devices are supplied with voltages for the operations of internal circuits for themselves. In designing such an internal voltage generator, a main issue is to constantly maintain an internal voltage at a desired level.
FIG. 1 is a circuit diagram of a conventional internal voltage generator.
Referring to FIG. 1, the internal voltage generator 100 includes first and second internal voltage driving units 110 and 120 configured to generate an internal voltage VINT corresponding to first and second reference voltages VREF_UP and VREF_DN. The first and second reference voltages VREF_UP and VREF_DN have equivalent voltage levels and correspond to a target voltage level of the internal voltage VINT.
The first internal voltage driving unit 110 includes a first comparator 112 and a pull-up driver 114. The first comparator 112 is configured to compare the first reference voltage VREF_UP with a fed-back voltage of the internal voltage VINT, and the pull-up driver 114 is configured to be driven in response to a first driving signal V1 outputted from the first comparator 112. The first comparator 112 is configured with a current mirror type differential amplifier, and the pull-up driver 114 is configured with a PMOS transistor coupled between a power supply voltage (VDD) terminal and an internal voltage (VINT) terminal and having a gate receiving the first driving signal V1 outputted from the first comparator 112.
The second internal voltage driving unit 120 includes a second comparator 122 and a pull-down driver 124. The second comparator 122 is configured to compare the second reference voltage VREF_DN with a fed-back voltage of the internal voltage VINT, and the pull-down driver 124 is configured to be driven in response to a second driving signal V2 outputted from the second comparator 122. The second comparator 122 is configured with a current mirror type differential amplifier, and the pull-down driver 124 is configured with an NMOS transistor coupled between the internal voltage (VINT) terminal and a ground voltage (VSS) terminal and having a gate receiving the second driving signal V2 outputted from the second comparator 122.
When a sink current ISINK flows out through a load circuit (not shown), the internal voltage generator 100 enables the first internal voltage driving unit 110 to pull up, i.e., charge, the internal voltage (VINT) terminal. On the other hand, when an output current ISOURCE flows in from the load circuit (not shown), the internal voltage generator 100 enables the second internal voltage driving unit 120 to pull down, i.e., discharge, the internal voltage (VINT) terminal. That is, the internal voltage generator 100 detects the voltage level of the internal voltage (VINT) terminal and maintains the target voltage at a constant level.
The internal voltage generator having the above-described configuration, however, has the following problems.
As described above, the first and second comparators 112 and 122 are configured with a differential amplifier. In such a differential amplifier, an offset error may be caused by process variations in the fabrication process. In this case, a direct current path may be formed between the pull-up driver 114 and the pull-down driver 124, as indicated by an arrow P of FIG. 1. For example, when an offset error occurs in the first and second comparators 112 and 122 in such a situation that the internal voltage must be maintained at 0.65 V, an output voltage VOUT_UP of the first internal voltage driving unit 110 may become 0.66 V, and an output voltage VOUT_DN of the second internal voltage driving unit 120 may become 0.64 V. Thus, the direct current path P may be formed to cause a current flow from the output voltage (VOUT_UP) terminal of the first internal voltage driving unit 110 to the output voltage (VOUT_DN) terminal of the second internal voltage driving unit 120. In this case, the first internal voltage driving unit 110 continuously outputs a charge current from the power supply voltage (VDD) terminal in order to adjust the output voltage VINT of the internal voltage generator 100 to 0.66 V. On the other hand, the second internal voltage driving unit 120 continuously sinks a discharge current to the ground voltage (VSS) terminal in order to adjust the output voltage VINT of the internal voltage generator 100 to 0.64 V. Consequently, the internal voltage generator 100 causes unnecessary power consumption.
To solve those problems, the second reference voltage VREF_DN of the second internal voltage driving unit 120 is set to be higher than the first reference voltage VREF_UP of the first internal voltage driving unit 110. Generally, the second reference voltage VREF_DN is set to be higher than the first reference voltage VREF_UP by approximately 40 mV.
In this case, the direct current path P is not formed, but a dead-zone may be formed. As illustrated in FIG. 2, the dead-zone refers to a zone where the internal voltage VINT of the internal voltage generator 100 is randomly distributed between the first reference voltage VREF_UP and the second reference voltage VREF_DN. Specifically, when a load current ISOURCE or ISINK is 0, the internal voltage VINT of the internal voltage generator 100 is probabilistically distributed within the dead-zone.
If the dead-zone is formed, the internal voltage VINT is not targeted to the desired voltage level. Consequently, speed and jitter characteristics of the circuit using the internal voltage VINT are degraded, thus causing a reduction in the yield of the semiconductor device.